VDD=VDDQ=1.5V

VDDSPD=3.0V to 3.6V

Fully differential clock inputs (CK, /CK) operation

Differential Data Strobe (DQS, /DQS)

On chip DLL align DQ, DQS and /DQS transition with CK transition

DM masks write data-in at the both rising and fallingedges of the data strobe

All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock

Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)supported

Programmable additive latency 0, CL-1 and CL-2 supported

Programmable CAS Write latency (CWL) = 5, 6, 7, 8

Programmable burst length 4/8 with both nibble sequential and interleave mode

BL switch on the fly

8 banks

8K refresh cycles /64ms

DDR3 SDRAM Package: JEDEC standard 82ball FBGA(x4/x8), 100ball FBGA(x16) with support balls

Driver strength selected by EMRS

Dynamic On Die Termination supported

Asynchronous RESET pin supported

ZQ calibration supported

TDQS (Termination Data Strobe) supported (x8 only)

Write Levelization supported

Auto Self Refresh supported

8 bit pre-fetch

This product is in compliance with the directive pertaining of RoHS