Przedmiotem sprzedazy jest chip OKI M6636

• Based on SAE-J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE (issued

August 12, 1991)

• CSMA/CD (Carrier-sense multiple access with collision detection)

• Internal transmit buffer (1 frame) and receive buffer (2 frames)

• Bit encoding: PWM (Pulse Width Modulation)

• Transmission Speed: 41.6K bps

• Multi-address setting with physical addressing: 1 type / functional addressing: 15 types

• Address filter function by multi-addressing (broadcasting possible)

• Automatic retransmission function by arbitration loss and non ACK

• 3 types of in-frame response support:

q Single-byte response from a single recipient

w Multi-byte response from a single recipient (with CRC code)

e Single-byte response from multiple recipients (ID response as ACK)

• Error detection by cyclic redundancy check (CRC)

• Various communication error detections

• Dual-wire bus abnormality detection by internal bus receiver and fault tolerance function

• Host CPU interface is LSB first / serial, 4 modes supported

q Clock synchronous serial (no parity)

Normal mode: 8-bit data

MPC Mode: 8-bit data + MPC bit (1: address / 0: data select bit)

w UART (yes/no parity selectable)

Normal mode: 1 start bit + 8-bit data + (parity) + 1 stop bit

MPC mode: 1 start bit + 8-bit data + MPC bit + (parity) + 1 stop bit

• Sleep Function

Low current consumption mode by oscillation stop (IDS Max < 50µA)

SLEEP / WAKE UP control from host CPU, WAKE UP via LAN bus

Kraj produkcji Thailandia

Przykładowe zastosowanie VAS5054A

Wystawiam paragon lub FV

ZAPRASZAM DO ZAKUPU