Specifications

PCI bus: 64-bit, 133/66MHz. These NICs support both PCI-X and PCI protocols, and can be used in any 3.3V PCI slot. In PCI-X mode, these NICs operate with bus frequencies from 75MHz to 133MHz. In PCI mode, these NICs operate at bus frequencies from 48MHz to 67MHz. The NIC is capable of peak PCI data rates at the limits of the PCI-X or PCI buses (1067MB/s for 64-bit, 133MHz PCI-X; 533 MB/s for 64-bit, 66MHz). However, the data rate to/from system memory will depend upon the host's memory and PCI-bus implementation. See this table for performance measurements on typical hosts. The NIC functions correctly in PCI-X slots that are compliant with PCI-X (version 1.0) specifications, and in 3.3V PCI slots (includes all 66MHz PCI slots) that are compliant with PCI specifications (version 2.2). The card is keyed for 3.3V operation only. PCI parity generation and detection is provided.

NIC processor: Lanai-2XP RISC operating at 333MHz. See the Lanai-X documentation linked from http://www.myri.com/vlsi/ for a complete description of the host-DMA, network-DMA, and copy/CRC engines that augment the RISC.

Local memory: 2MB (256Kx8B) in the -2 version; 4MB (512Kx8B) in the -4 version. The local memory operates from the same clock as the RISC. The 333MHz clock rate provides 2,664 MB/s of memory bandwidth for the RISC processor, the host-DMA engine, the network-DMA engines, and the copy/CRC engine. Byte parity is generated and checked.

EEPROM: 512KB, which includes the PCI-configuration-space data; Vital Product Data (VPD), including the serial number, MAC address, product code, and other information; initialization programs; and optionally self-test and bootstrap programs. The EEPROM can be re-programmed by the Lanai-2XP.

Myrinet-2000-Fiber port: 2.0+2.0 Gb/s data rate, 2.5+2.5 GBaud signaling, 8b/10b encoded Myrinet serial link (pdf, 60KB). An "LC" optical connector attaches to a fiber pair up to 200m of 50/125 multi-mode fiber. This is a Class 1 Laser Product (no biological hazard).

LEDs: The yellow (Lanai) LED on the PCI faceplate is controlled by the Lanai firmware; its interpretation is different for different Myrinet Control Programs. The green (link) LED on the PCI faceplate is off until the Lanai firmware is loaded and running. Thereafter, the green LED indicates the link state: off = not connected to an operating port; on = connected to an operating port; blinking = traffic.

Physical dimensions: Low-profile PCI short card: height 6.4cm (exclusive of the PCI faceplate), length 16.4cm (exclusive of the PCI faceplate), total thickness 2.2cm, weight 82g (including the standard PCI faceplate). The NIC can be supplied with either a standard PCI faceplate or a low-profile PCI faceplate.

Power: The NIC is powered from 3.3V from the PCI bus, 2.4A (8.0W) maximum for the -2 version, 2.0A (6.6W) for the -4 version.

Environmental: Operating: Temperature 0C to 55C up to 10,000 foot altitude. Relative humidity 15% to 80% @ 50C, non-condensing. Storage: Temperature -40C to 70C. Relative humidity 90% @ 65C.

Test connector: The test connector is used for Myricom's production testing, and should not be used in normal service.

Regulatory Approvals: Fully compliant with EN55024 (1998), EN61000-3-2 (2001), EN61000-3-3 (1995 W/A1: 98), EN55022 (1998) Class A, AS/NZS 3548 (1005 W/A1 & A2: 97) Class A, CISPR 22 (1997) Class A, FCC Part 15 Subpart B Section 15.109 Class A, VCCI (April 2000) Class A, & ICES-003 Class A (ANSI C63.4 1992). The M3F-PCIXF is a one-port variant of the M3F2-PCIXE two-port Myrinet/PCI-X NIC, with the same clock frequencies and circuit-board stackup. Its EMC characteristics are thus judged to be equivalent or better than the M3F2-PCIXE NICs. See this CE Declaration of Conformity and the EMC Test Report for the M3F2-PCIXE-2 NIC.

Myricom-supported software: Open source, distributed from the Myrinet Software & Customer Support page. These interfaces require the use of the GM-2 or MX software.

For customers who write their own Myrinet control programs, programmer's documentation is included in the Lanai-X chip documentation, linked from http://www.myri.com/vlsi/.

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