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Details of Intel Architecture Supported Features

The genuine Intel processor and surrounding native I/O capabilities of the Clanton SoC provides for a fully featured offering for both the maker community and students alike. It will also be useful to professional developers who are looking for a simple and cost effective development environment to the more complex Intel® Atom processor and Intel® Core processor-based designs.

• 400MHz 32-bit Intel® Pentium instruction set architecture (ISA)-compatible processor o 16 KBytes on-die L1 cache
  • 512 KBytes of on-die embedded SRAM
  • Simple to program: Single thread, single core, constant speed
  • ACPI compatible CPU sleep states supported
  • An integrated Real Time Clock (RTC), with an optional 3V “coin cell” battery for operation between turn on cycles.
• 10/100 Ethernet connector
• Full PCI Express* mini-card slot, with PCIe 2.0 compliant features
  • Works with half mini-PCIe cards with optional converter plate
  • Provides USB 2.0 Host Port at mini-PCIe connector
• USB 2.0 Host connector
  • Support up to 128 USB end point devices
• USB Device connector, used for programming
  • Beyond just a programming port - a fully compliant USB 2.0 Device controller
• 10-pin Standard JTAG header for debugging
• Reboot button to reboot the processor
• Reset button to reset the sketch and any attached shields
• Storage options:
  • Default - 8 MByte Legacy SPI Flash main purpose is to store the firmware (or bootloader) and the latest sketch. Between 256KByte and 512KByte is dedicated for sketch storage. The download will happen automatically from the development PC, so no action is required unless there is an upgrade that is being added to the firmware.
  • Default 512 KByte embedded SRAM, enabled by the firmware by default. No action required to use this feature.
  • Default 256 MByte DRAM, enabled by the firmware by default.
  • Optional micro SD card offers up to 32GByte of storage
  • USB storage works with any USB 2.0 compatible drive
  • 11 KByte EEPROM can be programmed via the EEPROM library.

Schematic, Reference Design & Pin Mapping

• Schematics: GalileoSchematic.pdf
• Cadence® Allegro® Files: GalileoReferenceDesign.zip

Dodatkowe informacje: http://arduino.cc/en/ArduinoCertified/IntelGalileo