| General information |
| Type |
CPU / Microprocessor |
| Market segment |
Mobile |
| Family |
Intel Core 2 Duo Mobile |
| Model number ? |
T7200 |
| CPU part numbers |
LF80537GF0414M is an OEM/tray microprocessor
BX80537T7200 is a boxed microprocessor |
| Frequency (MHz) ? |
2000 |
| Bus speed (MHz) ? |
667 |
| Clock multiplier ? |
12 |
| Package |
478-pin micro-FCPGA
1.38" x 1.38" (3.5 cm x 3.5 cm) |
| Socket |
Socket M |
| Introduction date |
Aug 28, 2006 |
| Price at introduction |
$294 |
| S-spec numbers |
| ES/QS processors |
Production processors |
| Part number |
QJEC |
QLZX |
QOLP |
QTCI |
SL9SF |
| BX80537T7200 |
+ |
| LF80537GF0414M |
+ |
+ |
+ |
+ |
+ |
|
| Architecture / Microarchitecture |
| Microarchitecture |
Core |
| Platform |
Napa Refresh |
| Processor core ? |
Merom |
| Core steppings ? |
B0 (QLZX)
B1 (QOLP)
B2 (QTCI, SL9SF) |
| CPUIDs |
6F4 (QLZX)
6F5 (QOLP)
6F6 (QTCI, SL9SF) |
| Manufacturing process |
0.065 micron |
| Data width |
64 bit |
| Number of cores |
2 |
| Floating Point Unit |
Integrated |
| Level 1 cache size ? |
2 x 32 KB instruction caches
2 x 32 KB write-back data caches |
| Level 2 cache size ? |
shared 4 MB |
| Features |
- MMX instruction set
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- EM64T technology ?
- Execute Disable Bit technology ?
- Virtualization Technology ?
|
| Low power features |
- Stop Grant mode ?
- Sleep mode ?
- Deep Sleep mode ?
- Deeper Sleep mode ?
- Enhanced Deeper Sleep mode ?
- Dynamic Cache sizing ?
- Enhanced SpeedStep technology ?
|
| Electrical/Thermal parameters |
| V core (V) ? |
1.0375 - 1.3 |
| Minimum/Maximum operating temperature (°C) ? |
0 - 100 |
| Maximum power dissipation (W) ? |
53.3 |
| Thermal Design Power (W) ? |
34 |
