dla porównania 7200 z npe-g1 lub g2 to zabawki ;), gdzie szyna to tylko 1,8 vs 5.......
juniper.net/techpubs/hardware/m5-m10/m5-m10-hwguide/m5-m10-hwguide.pdf
juniper.net/techpubs/hardware/m5-m10/m5-m10-rn/m5-m10-rn.pdf
juniper.net/techpubs/hardware/m5-m10/m5-m10-pic/m5-m10-pic.pdf
juniper.net/techpubs/hardware/m5-m10/m5-m10-install-poster/m5-m10-install-poster.pdf
The M5 and M10 routers include the router-specific Forwarding Engine Board (FEB) component that provides route lookup, filtering, and sampling, as well as switching to the destination Physical Interface Card (PIC). The FEB performs the function of the Flexible PIC Concentrators (FPCs) on other M-series routers. The FEB contains the Internet Processor II application-specific integrated circuit (ASIC), two distributed Buffer Manager ASICs, and two I/O Manager ASICs, and is responsible for making forwarding decisions, distributing packets throughout memory, and forwarding notification of outgoing packets.
The M5 and M10 routers provide a wide range of high-performance interfaces from T1 and E1 through OC12c/STM4 (for the M5 router) or OC48c/STM16 (for the M10 router). PICs between the two routers are interchangeable. For more information about supported PICs and FPCs for each M-series router type, see the appropriate PIC installation guide.
The M5 and M10 router Internet processor II ASIC forwards packets at a throughput rate of up to 5 Gbps for the M5 router and up to 10 plus Gbps for the M10 router. The ASIC technology provides such packet processing as rate limiting, filtering, and sampling of IP services.
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