| General information |
| Type |
CPU / Microprocessor |
| Market segment |
Mobile |
| Family |
AMD Turion 64 X2 Mobile technology |
| Model number ? |
TL-50 |
| CPU part numbers |
TMDTL50HAX4CT is an OEM/tray microprocessor
TMDTL50CTWOF is a boxed microprocessor |
| Stepping codes |
ADB5F CDB5F LDB4F LDB5F LDB8F LDBDF LDBGF LEDFF |
| Frequency ? |
1600 MHz |
| Clock multiplier ? |
8 |
| Package |
638-pin lidless micro-PGA |
| AMD Package number |
29262 |
| Socket |
Socket S1 (S1g1) |
| Size |
1.38" x 1.38" / 3.5cm x 3.5cm |
| Introduction date |
May 17, 2006 |
| Price at introduction |
$184 |
|
| Architecture / Microarchitecture |
| Microarchitecture |
K8 |
| Processor core ? |
Taylor |
| Core stepping ? |
F2 |
| Manufacturing process |
0.09 micron SOI |
| Data width |
64 bit |
| The number of cores |
2 |
| The number of threads |
2 |
| Floating Point Unit |
Integrated |
| Level 1 cache size ? |
2 x 64 KB 2-way associative instruction cache
2 x 64 KB 2-way associative data cache |
| Level 2 cache size ? |
2 x 256 KB 16-way associative exclusive cache |
| Physical memory |
1 TB |
| Virtual memory |
256 TB |
| Multiprocessing |
Uniprocessor |
| Features |
- MMX technology
- 3DNow!
- SSE
- SSE2
- SSE3
- AMD64 technology ?
- Virtualization technology ?
- Enhanced Virus Protection ?
|
| Low power features |
- Power Now!
- Deeper Sleep state ?
|
| On-chip peripherals |
- Dual-channel DDR2 SDRAM memory controller
- One 16-bit HyperTransport link with speeds up to 800 MHz
|
|
| Electrical/Thermal parameters |
| V core ? |
1.075V / 1.1V |
| Maximum operating temperature ? |
95°C |
| Thermal Design Power ? |
31 Watt |
