ValueRAM's 256M x 64-bit 2GB (2048MB) DDR3-1333 CL9 SDRAM (Synchronous DRAM)memory module, based on sixteen 128M x 8-bit DDR3-1333 FBGA components. The SPD is programmed to JEDEC standard latency 1333Mhz timing of 9-9-9 at 1.5V. This 240-pin DIMM uses gold contact fingers and requires +1.5V.
- DDR3-1333/PC-10600 JEDEC Spec (1333M Transfers/Sec and 10[zasłonięte]-10667 MB/Sec Peak Transfer Rate)
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JEDEC standard 1.5V +/- 0.075V Power Supply
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VDDQ = 1.5V +/- 0.075V
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667MHz IO Bus Clock to achieve DDR3-1333 Spec (1333M Transfers/Sec)
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8 independent internal bank
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Programmable CAS Latency: 5,6,7,8,9,10
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Posted CAS
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Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
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Programmable CAS Write Latency(CWL) = 9
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8-bit pre-fetch
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Burst Length: 8 (Interleave without any limit, sequential with starting address 000 only), 4 with tCCD = 4
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which does not allow seamless read or write [either on the fly using A12 or MRS]
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Bi-directional Differential Data Strobe
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Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm +/- 1%)
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On Die Termination using ODT pin
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Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE . 95°C
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Asynchronous Reset
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1066Mbps CL7 doesnt have backward compatibility with 800Mbps CL5
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PCB : Height 1.180 (30.00mm), double sided component